FPGA中的多时钟域设计

FPGA中的多时钟域设计

觉得这篇文章很好，因此在这里翻译一下——或者也可以说是按我的理解加中文注释。

Problem #1: Meta-stability

On a truly asynchronous clock boundary, the receiving domain's clock is used to capture each signal from the driving domain in a flip-flop. Because there is no defined temporal relationship between the clock and the signal, it is entirely possible that they could transition at the same time. Whenever this happens, there is a possibility of meta-stability in the receiving clock domain. 在设计中，常常会用一个触发器接收来自于另一个时钟域的输出信号(即用本地时钟的前沿来锁存另一个时钟域的信号）。由于触发器的时钟和数据输入信号不存在确定的相位关系，因此完全有可能出现数据和时钟同时跳变的情况。这样，就在接收端所在的时钟域中造成了亚稳态。

Problem #2: Reset synchronization 复位的同步问题 Improper synchronization of reset signals is a related problem in multi-clock designs. Designers sometimes forget that reset signals are subject to meta-stability and must be protected by synchronizers. Generally, the entire SoC can be reset by a single signal, which therefore must propagate to all clocked elements in all clock domains. 复位信号的不同步，也是一个与多时钟设计相关的问题。设计者有时候会忘了一个事实，那就是复位信号也可能引起亚稳态问题，而且必须用synchronizers来对它进行同步。通常来说，每个SOC都会有一个reset信号，这个信号被送到各个时钟域的各个同步逻辑单元，来对整个芯片/系统进行复位。

There is no need for synchronization on the activation edge of reset, since by definition all state elements are reset to initial values, and the reset signal will generally be held active for enough cycles to allow any meta-stability to settle out.

版权声明：本文内容由网络用户投稿，版权归原作者所有，本站不拥有其著作权，亦不承担相应法律责任。如果您发现本站中有涉嫌抄袭或描述失实的内容，请联系我们jiasou666@gmail.com 处理，核实后本网站将在24小时内删除侵权内容。