宽带数据转换器应用的JESD204B与串行LVDS接口考量

宽带数据转换器应用的JESD204B与串行LVDS接口考量

Abstract

摘要

Some key end-system applications that are driving the deployment of this specification， as well as a contrast between serial low voltage differential signaling （LVDS） and JESD204B， are the subject of the remainder of the article.

本文余下篇幅将探讨推动该规范发展的某些关键的终端系统应用，以及串行低压差分信号（LVDS）和JESD204B的对比。

Figure 1. Typical high speed converter to FGPA interconnect configurations using JESD204A/JESD204B interfacing （Source： Xilinx®）。

图1.使用JESD204A/JESD204B接口的典型高速转换器至FGPA互连配置（来源：Xilinx®）。

The Applications Driving the Need for JESD204B

应用推动对JESD204B的需求

Wireless Infrastructure Transceivers

目前无线基础设施收发器采用LTE等基于OFDM的技术，这类技术使用部署FPGA或SoC器件的DSP模块，通过驱动天线阵列元件，单独为每个用户的手机产生波束。在发射和接收模式下，每个阵列元件每秒可能需要在FPGA和数据转换器之间传输数百兆字节的数据。

Software-Defined Radios

Today’s software-defined radios utilize advanced modulation schemes that can be reconfigured on the fly， and rapidly increasing channel bandwidths， to deliver unprecedented wireless data rates. Efficient， low power， low pin count FPGA-to-data converter interfaces in the antenna path play a critical role in their performance. Software-defined radio architectures are integral to the transceiver infrastructure for multicarrier， multimode wireless networks supporting GSM， EDGE， W-CDMA， LTE， CDMA2000， WiMAX， and TD-SCDMA.

当今的软件定义无线电技术利用先进的调制方案，可即时重配置，并极大地增加了通道带宽，提供最佳的无线数据速率。天线路径中高效、低功耗、低引脚数的FPGA至数据转换器接口对性能起着决定性的作用。软件定义无线电架构已与收发器基础设施相整合，用于多载波、多模无线网络，支持GSM、EDGE、W-CDMA、LTE、CDMA2000、WiMAX和TD-SCDMA。

Medical Imaging Systems

医疗成像系统

Medical imaging systems including ultrasound， computational tomography （CT） scanners， magnetic resonance imaging （MRI）， and others generate many channels of data that flow through a data converter to FPGAs or DSPs. Continually increasing I/O counts are driving up the number of components by requiring the use of interposers to match FPGA and converter pin out and increasing PCB complexity. This adds additional cost and complexity to the customer’s system that can be solved by the more efficient JESD204B interface.

Radar and Secure Communications

雷达和安全通信

Serial LVDS vs. JESD204B

串行LVDS与JESD204B的对比

Choosing Between Series LVDS and JESD204B Interface

在串行LVDS和JESD204B接口之间选择

In order to best select between converter products that use either LVDS or the various versions of the JESD204 serial interface specification， a comparison of the features and capabilities of each interface is useful. A short tabular comparison is provided in Table 1. At the SERDES level， a notable difference between LVDS and JESD204 is the lane data rate， with JESD204 supporting greater than three times the serial link speed per lane when compared with LVDS. When comparing the high level features like multidevice synchronization， deterministic latency， and harmonic clocking， JESD204B is the only interface that provides this functionality. Systems requiring wide bandwidth multichannel converters that are sensitive to deterministic latency across all lanes and channels won’t be able to effectively use LVDS or parallel CMOS.

Table 1. Comparison Between Serial LVDS and JESD204 Specifications

表1.串行LVDS和JESD204规范对比

LVDS Overview

LVDS概述

LVDS是连接数据转换器与FPGA或DSP的传统方法。LVDS于1994发布，目标在于提供比已有的RS-422和RS-485差分传输标准更高的带宽和更低的功耗。随着1995年TIA/EIA-644的发布，LVDS成为标准。二十世纪90年代末，LVDS的使用率上升，并随着2001年TIA/EIA-644-A的发布，LVDS标准亦发布了修订版。

The huge increase in the number and speed of data channels between FPGAs or DSPs and data converters， particularly in the applications described earlier， has created several issues with the LVDS interface （see Figure 2）。 The bandwidth of a differential LVDS wire is limited to about 1.0 Gbps in the real world. In many current applications， this creates the need for a substantial number of high bandwidth PCB interconnects， each of which is a potential failure point. The large number of traces also increases PCB complexity or overall form factor， which raises both design and manufacturing costs. In some applications， the data converter interface becomes the limiting factor in achieving the required system performance in bandwidth hungry applications.

FPGA或DSP与数据转换器间数据通道和速度的大幅增长——尤其是前文讨论的那些应用——使LVDS接口暴露了一些问题（见图2）。现实中，差分LVDS线的带宽限制在1.0 Gbps左右。在目前很多应用中，这一限制导致需要许多高带宽PCB互连，而每一处都有可能出故障。大量的走线还增加了PCB的复杂性或整体尺寸，导致设计和制造成本上升。在某些带宽需求量巨大的应用中，数据转换器接口已成为满足所需系统性能的制约因素。

Figure 2. Challenges in system design and interconnect using parallel CMOS or LVDS.

图2.使用并行CMOS或LVDS带来的系统设计与互连的挑战。

JESD204B OVERVIEW

JESD204B概述

The JESD204 data converter serial interface standard was created by the JEDEC Solid State Technology Association JC-16 Committee on Interface Technology with the goal of providing a higher speed serial interface for data converters to increase bandwidth and reduce the number of digital inputs and outputs between high speed data converters and other devices. The standard builds on 8b/10b encoding technology developed by IBM that eliminates the need for a frame clock and a data clock， enabling single line pair communications at a much higher speed.

JESD204数据转换器串行接口标准由JEDEC固态技术协会JC-16接口技术委员会建立，目标是提供速率更高的串行接口、提升带宽并降低高速数据转换器和其他器件之间的数字输入和输出通道数。该标准的基础是IBM开发的8b/10b编码技术，它无需帧时钟和数据时钟，支持以更高的速率进行单线对通信。

In 2006， JEDEC published the JESD204 specification for a single 3.125 Gbps data lane. The JESD204 interface is self-synchronous， so there is no need to calibrate the length of the PCB wire traces to avoid clock skew. JESD204 leverages the SERDES ports offered on many FPGAs to free up general- purpose I/O.

JESD204A于2008年发布，增加了对多路时序一致数据通道和通道同步的支持。这种增强使得使用更高带宽的数据转换器和多路同步数据转换器通道成为可能，并且对用于蜂窝基站的无线基础设施收发器尤为重要。JESD204A还提供多器件同步支持，这有利于医疗成像系统等使用大量ADC的应用。

JESD204B， the third revision of the spec， increases the maximum lane rate to 12.5 Gbps. JESD204B also adds deterministic latency， which communicates synchronization status between the receiver and transmitter. Harmonic clocking， also introduced in JESD204B， makes it possible to derive a high speed data converter clock from a lower speed input clock with deterministic phasing.

JESD204B是该规范的第三个修订版，将最大通道速率提升至12.5 Gbps。JESD204B还增加了对确定延迟的支持，该功能可在接收器和发射器之间进行同步状态的通信。JESD204B还支持谐波时钟，使得依据确定相位，通过低速输入时钟获得高速数据转换器时钟成为可能。

Conclusion

结论

The JESD204B industry serial interface standard reduces the number of digital inputs and outputs between high speed data converters and FPGAs and other devices. Fewer interconnects simplify layout and make it possible to achieve a smaller form factor （see Figure 3）。 These advantages are important for a wide range of high speed data converter applications， such as wireless infrastructure transceivers， software-defined radios， medical imaging systems， and radar and secure communications. Analog Devices is an original participating member of the JESD204 standards committee and we have concurrently developed compliant data converter technology and tools along with a comprehensive product roadmap offering. By providing customers with products that combine our cutting edge data converter technology along with the JESD204A/JESD204B interface， we expect to enable customers to solve their system design problems， while taking advantage of this significant interfacing breakthrough.

Figure 3. JESD204 with its high speed serial I/O capability solves the system PCB complexity challenge.

图3.JESD204具有高速串行I/O能力，能够解决系统PCB复杂性挑战。

About the Author

George Diniz is a product line manager in the High Speed Digital- to-Analog Converters Group at Analog Devices in Greensboro， NC. He leads a team responsible for the development of JESD204B receiver and transceiver interface cores， which are integrated into high speed analog-to-digital and digital-to-analog converter products. He has 25 years of experience in the semiconductor industry and has held various roles in design engineering and product line management. Before joining ADI， George was a design engineer at IBM， where he was engaged in mixed-signal design of custom SRAM macros， PLL， and DLL functions for power PC processors. He has an M.S.E.E. from North Carolina State University and a B.S.E.E. from Manhattan College. For recreation， George enjoys outdoor activities， restoring automobiles， and running. He can be reached at george.diniz@analog.com.

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